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From: grege@gold.GVG.TEK.COM (Greg Ebert)
Newsgroups: comp.lsi
Subject: Re: edge triggered or self-clocked logic(?)
Keywords: edge triggered logic vlsi self-clocked
Message-ID: <1489@gold.GVG.TEK.COM>
Date: 24 Sep 90 21:23:23 GMT
References: <1990Sep24.195751.14603@news.iastate.edu>
Distribution: usa
Organization: Grass Valley Group, Grass Valley, CA
Lines: 27


 mpurtell@iastate.edu (Purtell Michael J) writes:

>I'm in a VLSI class where we'll each be doing a full custom design for our
>final project 

I could tell you a horror story about my full-custom chip I did at UCLA...

>and I'm exploring the possibility of using edge triggered
>or self-clocked(?) logic in the design (A Mandelbrot set generator,
>this point).

I've been designing chips for over 5 years, and I'll swear by using fully-
synchronous logic. Self-clocked logic IS feasible and DOES work, but you
have to be extremely careful with timing. A mandelbrot generator is a
rather complicated device, and you have a (very) limited amount of time
to get this thing designed, entered, rule-checked, simulated, debugged,
analyzed, fabricated, and tested.

#ifdef SERMON
I don't mean this sarcastically, but good luck. I was still working on mine
during finals week and seriously considered not taking my history final so
I could work on my chip (why take an exam you didn't have time to study for ?)

Chip design is fun and challenging. Don't try to burn yourself out now, because
there will be plenty of opportunity for that on-the-job.
#endif