Path: utzoo!attcan!uunet!samsung!uakari.primate.wisc.edu!dali.cs.montana.edu!milton!uw-beaver!sumax!ole!sss
From: sss@ole.UUCP (Stephen Sugiyama)
Newsgroups: comp.lsi.cad
Subject: Re: VLSI Technology place and route tools for gate arrays
Message-ID: <1669@ole.UUCP>
Date: 20 Sep 90 15:27:02 GMT
References: <4470@optilink.UUCP> <1990Sep18.151012.1177@arnor.uucp>
Reply-To: sss@ole.UUCP (Stephen Sugiyama)
Organization: Seattle Silicon Corporation, Bellevue, WA.
Lines: 35

dgreen@cs.ucla.edu writes:
> manley@optilink.UUCP (Dave Manley) writes:
> 
> |> Has anyone out there had personal experience with these tools and
> |> could they comment on the following points:
> |> 
> |> Do (can) the placement tools use the hierarchical netlist to obtain a
> |> better placement than is available from the flattened netlist?  I
> |> assume the extra information in the hierarchical netlist could be
> |> used to do this?
> 
> Some commercial tools do use the hierarchy to help place the circuits.
> I believe that Seattle Silicon's product, for example, does this.

Well, not exactly.  The Seattle Silicon tools (which are cell-based, not
for gate arrays) work off of a flattened netlist, except that tool-specific
cells (Datapath, e.g.) are partitioned based on inherited properties from the
schematic.

I think Dave Manley was asking specifically about the gate array tools
from VLSI Technology: I don't know the details of their tools (hi Sunil)
but I suspect that their "Gate Assistant" floorplanning tool uses hierarchy
to define blocks.  I doubt that any further hierarchy information is
used in the placement.

> However, it isn't all that clear that using the hierarchy necessarily
> helps.  In some cases, yes.  In others, no.

This is a good point; also note that a "better placement" doesn't nessarily
mean one that is smaller in area.

-- 
Stephen Sugiyama
...uw-beaver!sumax!ole!sss
ole!sss@beaver.cs.washington.edu