Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!yale!mintaka!masala!shers
From: shers@masala.lcs.mit.edu (Alexander The Great)
Newsgroups: comp.lsi.cad
Subject: Re: checking sim files
Message-ID: <1990Sep21.232209.28404@mintaka.lcs.mit.edu>
Date: 21 Sep 90 23:22:09 GMT
References: <38779@ucbvax.BERKELEY.EDU>
Sender: daemon@mintaka.lcs.mit.edu (Lucifer Maleficius)
Organization: MIT Laboratory for Computer Science
Lines: 27

In article <38779@ucbvax.BERKELEY.EDU> holmer@ernie.Berkeley.EDU (Bruce K. Holmer) writes:
#
#The following is a set of Unix command lines (and small awk programs)
#that I have found helpful in checking a layout for unconnected nodes
#(a typical error in hand layout).  These scripts assume a CMOS sim
#file with no aliases (our layout CAD tools can generate this
#directly).  For those of you who have an alias file after extraction,
#you would need to preprocess the sim file to substitute a unique name
#for each node.
#
#I'd be interested in finding out if there are more sophisticated tools
#for discovering typical layout errors (either using Magic or sim as
#input).
#
#Enjoy,
#--Bruce
#
This code is a nice thing to keep around, but using the switch level simulator
while debugging the logic (digital chips only, of course) catches these
unconnected nodes as well.

Alex
--
+-------------------------------+------+-----------------+---------------------+
|Alexander The Great Sherstinsky|me    |shers@caf.mit.edu|To become as refined |
|Alexander Semyon Sherstinsky   |myself|shers@caf.mit.edu|a person as possible.|
|Alex Sherstinsky               |I     |shers@caf.mit.edu|*********************|