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From: holmer@ernie.Berkeley.EDU (Bruce K. Holmer)
Newsgroups: comp.lsi.cad
Subject: Re: checking sim files
Message-ID: <38798@ucbvax.BERKELEY.EDU>
Date: 22 Sep 90 06:41:28 GMT
References: <38779@ucbvax.BERKELEY.EDU> <1990Sep21.232209.28404@mintaka.lcs.mit.edu>
Sender: usenet@ucbvax.BERKELEY.EDU
Reply-To: holmer@ernie.Berkeley.EDU.UUCP (Bruce K. Holmer)
Organization: University of California, Berkeley
Lines: 22

In article <1990Sep21.232209.28404@mintaka.lcs.mit.edu> shers@masala.lcs.mit.edu (Alexander The Great) writes:
>This code is a nice thing to keep around, but using the switch level simulator
>while debugging the logic (digital chips only, of course) catches these
>unconnected nodes as well.

You are absolutely correct.

The principal time to use the scripts is just after layout has
completed and before switch level simulation starts in earnest.  The
chip we designed has 110,000 transistors and took overnight to
reextract.  The first run of the scripts found 137 unconnected wires.
This saved us several days of tracing back X's in esim and
reextraction.  However, we spent weeks tracing down other errors:
wrong gates, missing inverters, extra inverters, swapped wires, bus
contention, etc.  So the conclusion is that the scripts save a small
but non-trival amount of time.

I forgot to mention in the original article that sort uses /tmp to
store intermediate results.  If you have a big chip, /tmp may not have
enough room.  Use sort's -T option to get around this.

--Bruce