Path: utzoo!attcan!uunet!wuarchive!usc!ucsd!ucrmath!rhyde
From: rhyde@ucrmath.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: Sculley letter (was: Low Blow from Apple)
Message-ID: <8830@ucrmath.ucr.edu>
Date: 23 Sep 90 18:35:23 GMT
References: <794@mtune.ATT.COM> <13924@smoke.BRL.MIL>
Organization: University of California, Riverside
Lines: 19


The 68xxx architecture is not maxed out.  Witness the 68040.  Three years
ago RISC proponents would not have believed that the 68xxx or 80x86 families
would be capable of 15-20 MIPS.  RISC's performance boost over CISC is dubious
at best.  As for RISC's inherent scalability, technology will probably guarantee
that RISC does not pull much ahead of CISC.  The next generation of chips
(68050, 80586, 32764, etc.) will probably pull ahead, or at least match the
MIPS performance of SPARC, R3000, etc.  Personally, I'd rather have 30 CISC
MIPS than 30 RISC MIPS.  The trend you see was based on design decisions from
2-3 years ago.  I think the current crop of CISC processors are beginning to
show that those design decisions were not the best.

DOS windows on the SUN equipment actually runs faster on the 68xxx boxes than
on the SPARC.  Using RISC to emulate a 65c816 probably wouldn't be as good as
using a 68040.  Perhaps Apple dragging their feet on a RISC system isn't too
bad.  By the time they would actually ship something, the 68040/68050 boxes
would be just as fast.  And emulating a GS on those machines would probably be
even better (not to mention, you could run Mac software).
*** Randy Hyde O-)