Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!zaphod.mps.ohio-state.edu!wuarchive!mit-eddie!rutgers!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.sys.atari.st
Subject: Re: TT RAM
Message-ID: <14673@cbmvax.commodore.com>
Date: 26 Sep 90 21:07:23 GMT
References: <3107@medusa.informatik.uni-erlangen.de> <2304@atari.UUCP> <22218@grebyn.com>
Reply-To: daveh@cbmvax.commodore.com (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 28

In article <22218@grebyn.com> ckp@grebyn.UUCP (Checkpoint Technologies) writes:
>In article <2304@atari.UUCP> apratt@atari.UUCP (Allan Pratt) writes:
>>The MMU is used, however, so don't mess with it.  It's used to get around 
>>a bug in the 68030's design; I may explain in more detail later.

>Well, you got me curious, so go ahead and explain it.  There's a bug
>in the 68030 design that can be fixed via the MMU?  Is it perhaps
>related to the behavior of the instruction and data caches?

It's a data cache anomaly.  There are two data caching modes, standard and
write allocate; the latter is required for cache consistency when user and
supervisor data spaces access the same logical memory.  However, in write
allocate mode, the data cache is updated on writes.  If you write a longword
aligned longword to a longword port, the cache entry is marked valid.  In 
all modes, the write cycle ignores the CIIN* signal (hardware driven cache
inhibit), so this can be a problem in dealing with things like 32 bit I/O
registers, since you'll end up caching the register even if hardware tries
to inhibit such caching (which would be natural for any I/O operation).
While there are several ways around this problem, the simplest is to use the
MMU and make all your I/O pages uncachable.  The caches always obey the MMU
table entry...

>First comes the logo: C H E C K P O I N T  T E C H N O L O G I E S      / /  

-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
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	Standing on the shoulders of giants leaves me cold	-REM