Xref: utzoo comp.sys.atari.st:31145 comp.sys.atari.st.tech:364 Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!rutgers!cbmvax!daveh From: daveh@cbmvax.commodore.com (Dave Haynie) Newsgroups: comp.sys.atari.st,comp.sys.atari.st.tech Subject: Re: 68030 cache, write-allocate, and everything. Message-ID: <14623@cbmvax.commodore.com> Date: 24 Sep 90 19:30:28 GMT References: <2308@atari.UUCP> <34208@cup.portal.com> Reply-To: daveh@cbmvax.commodore.com (Dave Haynie) Distribution: na Organization: Commodore, West Chester, PA Lines: 26 In article <34208@cup.portal.com> buggs@cup.portal.com (William Edward JuneJr) writes: > >Allen@atari, >I don't understand the RAM situation in the TT. ST Report says that to run > the TT @ 32 MHz you'd need 50nsec DRAMS. To run any 32 MHz 68030 at 0 wait states, you need a memory chip that can CYCLE in about 60ns. Even a 50ns DRAM isn't fast enough for a 32MHz 68030; you would need something on the order of 20-30ns SRAM. So, like most 68030 systems going above 12-16MHz or so, they add wait states. The number of clocks per memory access, more than the clock speed, will give you a clue as to the effective speed of a TT. >There isn't a cache, it's on the '030, right? There are separate, 256 byte, direct mapped caches on the 68030, one each for instructions and data. >Ed June -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM