Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!newstop!exodus!shukra.Eng.Sun.COM!ram
From: ram@shukra.Eng.Sun.COM (Renu Raman)
Newsgroups: comp.arch
Subject: Re: Cache Line Fills -- Critical Word First
Message-ID: <987@exodus.Eng.Sun.COM>
Date: 27 Sep 90 08:06:16 GMT
References: <34275@cup.portal.com>
Sender: news@exodus.Eng.Sun.COM
Organization: Sun Microsystems, Mt. View, Ca.
Lines: 10

In article <34275@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes:
>sequential order.  I believe the MIPS R6000 is an example of this.
>in the order 1-0-3-2.  On SPARC or the 68040, the read continues to the end
>of the block and wrapsaround, i.e. 1-2-3-0.

On a SPARC!!! Let's be specific, since there are various SPARC
processors and different  systems built out of these various SPARC processors.

To date, there aren't any Systems built with Sparc processors that have
caches which do wrap-around-fill that I know of...