Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!olivea!mintaka!snorkelwacker!usc!julius.cs.uiuc.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@crhc.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: Cache Line Fills -- Critical Word First Message-ID: Date: 28 Sep 90 18:02:07 GMT References: <34275@cup.portal.com> <987@exodus.Eng.Sun.COM> <34342@cup.portal.com> Sender: news@ux1.cso.uiuc.edu (News) Organization: Center for Reliable and High-Performance Computing University of Illinois at Urbana Champaign Lines: 9 In-Reply-To: mmm@cup.portal.com's message of 28 Sep 90 05:39:57 GMT ..> Critical word first, wrap around fill (1230) and other orders (1032) Trying to generalize: Perhaps a bus specification should not include the size of the wrap-around region; rather, the control for the burst should specify which address bits get complimented at which cycle of the burst? -- Andy Glew, a-glew@uiuc.edu [get ph nameserver from uxc.cso.uiuc.edu:net/qi]