Path: utzoo!attcan!uunet!nih-csl!lhc!mimsy!midway!linac!pacific.mps.ohio-state.edu!zaphod.mps.ohio-state.edu!usc!apple!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch
Subject: Re: Cache Line Fills -- Critical Word First
Message-ID: <34342@cup.portal.com>
Date: 28 Sep 90 05:39:57 GMT
References: <34275@cup.portal.com> <987@exodus.Eng.Sun.COM>
Organization: The Portal System (TM)
Lines: 21

ram@shukra.Eng.Sun.COM (Renu Raman) says:

> On a SPARC!!! Let's be specific, since there are various SPARC
> processors and different  systems built out of these various SPARC processors.
> 
> To date, there aren't any Systems built with Sparc processors that have
> caches which do wrap-around-fill that I know of...

In the specification of the SBus (the bus on the SPARCstation 1), the order for
a burst transfer is to read to the end of the aligned block, then wraparound
to the beginning.  I don't have the MBus spec -- perhaps you could tell
us whether that requires the same burst order.

If the architecture of SPARC or its standard buses require this burst order,
then it is probably accurate to say that all present and future SPARC
implementations are non-optimal with regard to their burst order -- a problem
solved successfully in the Intel 486  :-)

This is symptomatic of the area in which Sun is weakest -- lack of attention
to details.  I could say some choice words about the %&*#@ optical mouse
on the Sun, but that would be getting off the topic ....