Path: utzoo!attcan!uunet!auspex!guy
From: guy@auspex.auspex.com (Guy Harris)
Newsgroups: comp.arch
Subject: Re: Cache Line Fills -- Critical Word First
Message-ID: <4124@auspex.auspex.com>
Date: 1 Oct 90 17:11:15 GMT
References: <34275@cup.portal.com> <987@exodus.Eng.Sun.COM> <34342@cup.portal.com>
Organization: Auspex Systems, Santa Clara
Lines: 13

>In the specification of the SBus (the bus on the SPARCstation 1), the order for
>a burst transfer is to read to the end of the aligned block, then wraparound
>to the beginning.  I don't have the MBus spec -- perhaps you could tell
>us whether that requires the same burst order.

I asked somebody here, and he said:

  I quote from the Mbus Spec:

  "Mbus supports a feature called wrapping. During the address phase, MAD[2:0]
  is a don't care, and MAD[35:3] defines the 32 bytes to be returned. As the
  data is is returned, the MAD[4:3] is incremented by the memory controller,
  producing a wrap-around effect."