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From: jesup@cbmvax.commodore.com (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: Cache Line Fills -- Critical Word First
Message-ID: <14780@cbmvax.commodore.com>
Date: 1 Oct 90 23:54:36 GMT
References: <34275@cup.portal.com>
Reply-To: jesup@cbmvax.commodore.com (Randell Jesup)
Organization: Commodore, West Chester, PA
Lines: 22

In article <34275@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes:
>For example, if the miss is on address xxx1, the 486 will fill the cache line
>in the order 1-0-3-2.  On SPARC or the 68040, the read continues to the end
>of the block and wrapsaround, i.e. 1-2-3-0.

>Does this little design tweak pay off?  Just recently, Motorola has provided
>proof!  They've introduced two static RAM's with on-chip burst control logic
>optimized for use as cache memories.  The MCM62940 is compatible with
>conventional burst ordering.  The MCM62486 uses Intel-style burst ordering.
>The MCM62940 is offered in the following speed grades: 15, 20, and 25 ns.
>(Max. access time.)  The MCM62486 is offered in:  14, 19, and 24 ns.  Intel
>wins by a nanosecond!

	However, does having to wait for the last word of the burst for the
next entry (#2) cost you anything?  For instructions at least, there is
a definite tendency towards consecutive access (and even somewhat in data,
when operating on blocks such as strings or copies).

-- 
Randell Jesup, Keeper of AmigaDos, Commodore Engineering.
{uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com  BIX: rjesup  
Common phrase heard at Amiga Devcon '89: "It's in there!"