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From: tim@proton.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Cache Line Fills -- Critical Word First
Message-ID: <1990Oct3.140725.3931@mozart.amd.com>
Date: 3 Oct 90 14:07:25 GMT
References: <34275@cup.portal.com> <14780@cbmvax.commodore.com> <41856@mips.mips.COM>
Sender: usenet@mozart.amd.com (Usenet News)
Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc., Austin, Texas
Lines: 32

In article <41856@mips.mips.COM> mash@mips.COM (John Mashey) writes:
| For the I-cache, when you have a cache miss:
| 	I1) You can stall the machine, fetch the entire cache block,
| 	then restart.  This is clearly the simplest.
| 	I2) You can do "early restart", where you begin executing as soon
| 	as the requested word is available.  This is sometimes called
| 	"Instruction Streaming" (in the MIPS R3000), i.e.,  when you
| 	cache miss:
| 		start fetching at word 0 of the block
| 		stall until the needed word is fetched, then stream
| 		if you branch elsewhere before the end of the block,
| 		stop streaming, stall the pipeline until block filled
| 		also, if a load/store causes a cache miss, complete
| 		the I-cache refill, then handle the D-cache miss
| 	I3) You can do "out-of-order fetch" in addition to early restart,
| 	and then do "wrapped fetch", so that you wrap-around to complete.

There are also other possibilities, such as:

	I4) Have a valid bit per word in the cache block, and fetch
	    the missed instruction first, then burst reload continuing
	    from that instruction into subsequent blocks, rather than
	    wrapping around to complete the missed block.

This tends to match instruction fetch patterns better than the other
solutions, but with the added expense of extra valid bits and more
complexity.


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)