Path: utzoo!attcan!uunet!ns-mx!pyrite.cs.uiowa.edu
From: jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879)
Newsgroups: comp.arch
Subject: Re: Looking for a really odd computer
Message-ID: <2515@ns-mx.uiowa.edu>
Date: 3 Oct 90 19:55:36 GMT
References: <2721@crdos1.crd.ge.COM>
Sender: news@ns-mx.uiowa.edu
Lines: 42

From article <2721@crdos1.crd.ge.COM>,
by davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr):
> 
>                                                                ... The
> question is, has anyone ever made a general purpose computer with and
> odd word size? No one doesn't count, thank you bit slicers.
> 
Back in the days of the DEC-10, a 36 bit machine, the byte size was
whatever you wanted (the DEC-10 had byte manipulation instructions that
allowed any size, although 6 and 9 were the popular ones because they
divided evenly into 36.

The wierdest word-size I've seen was an early proposal for the ILLIAC II,
written, I think, by Don Gillies.  Someone with access to the tech reports
from the U of Illinois back in the 1950's might be able to find it.  The
proposal called for a 53 bit word made of four 13 bit bytes and a sign
bit.  This is the only serious proposal I can remember seeing that had a
prime number of bits per word (discounting oddities with one or two bits
per word).

ILLIAC II Instructions in this proposal were to be two bytes each, with a
main memory address of one byte (8K 53 bit words is, after all, a
reasonable memory size by the standards of the 1950's).  One of the most
interesting parts of the proposal was a loop control instruction that
referenced a loop control word with something like the following fields
(one byte each):

  loop counter (in the least significant byte)
  amount to increment counter by
  final value of loop counter
  location to branch to if loop counter not equal to final value

Indexing was only supposed to use the least significant byte of the loop
counter, so the loop control register could also be used as an index
register.  The loop control instruction could update the counter, compare
it with the final value, and do the conditional branch in parallel, all in
one instruction cycle.

If memory serves me correctly, ILLIAC II was built as a 48 bit machine,
a far less interesting word size.
					Doug Jones
					jones@herky.cs.uiowa.edu