Path: utzoo!attcan!uunet!wuarchive!zaphod.mps.ohio-state.edu!swrinde!emory!hubcap!hades
From: hades@uni-paderborn.de (Hans-Detlef Siewert)
Newsgroups: comp.parallel
Subject: Request for information about simulating VLIW architectures
Keywords: vliw, parallel, pipelining
Message-ID: <10780@hubcap.clemson.edu>
Date: 4 Oct 90 15:35:49 GMT
Sender: fpst@hubcap.clemson.edu
Organization: Uni-GH Paderborn, West Germany
Lines: 18
Approved: parallel@hubcap.clemson.edu


 I am interesting in simulating machines with a parallel VLIW
architecture. The simulator should be capable to handle descriptions
of different processors (i860, 88000, TRACE,... but also imaginary
models) and to simulate programs for them with a graphical user
interface (under X-Windows).
 I would be grateful if someone could send me information or
references for simulation of VLIW architectures and pipelining.

	Many thanks in advance
		Hans-Detlef Siewert

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/**\  Hans-Detlef Siewert, CS student at UGHS Paderborn
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