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From: rhyde@ucrmath.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: RISC Machines
Message-ID: <8971@ucrmath.ucr.edu>
Date: 29 Sep 90 20:59:55 GMT
References: <8139.apple.net@pro-angmar> <13963@smoke.BRL.MIL>
Organization: University of California, Riverside
Lines: 29

>>> its opcodes follow no regular pattern...

Oh yes they do!  It may not appear regular to the unaided eye, but the
addressing modes are represented by various bit fields in the opcode and
the basic instructions themselves are represented by other bitfields.
Finally, the class of the instruction (I seem to recall that there were
four basic groups) were represented by another set of bits.

>>> The 6502 is accumulator-oriented...

True, it's an accumulator machine, but I've never heard this term used when
comparing whether the machine is RISC or CISC before!

At the time the 6501 (yes, "1") was developed, the engineers were very
interested in reducing the size of the instruction set.  Chips like the
8080 and 6800 were selling for over $100.  MOS Technologies wanted to sell
their chip for $20.  To do so, they needed to reduce the die size tremendously.
(The size of the die was a direct factor in the cost of the chip back then).
Therefore, they reduced the number of instructions present in the instruction
set which directly reduced the size of the die (ever wonder why there aren't
any ADD, SUB, signed branches, and other instructions common on CPUs back in
1976?).  In this respect, I guess you could all the 6502 a "RISC" chip.
OTOH, they also REDUCED the number of REGISTERS on the chip (compared to the
6502's peers) and increased the number of memory addressing modes (I do not
consider direct page MEMORY locations registers, it is a shortened memory
addressing mode (available on other processors like the 68000 and 8086)).
At the time, the 6502, indeed, was considered the most CISC-like architecture
around.
*** Randy Hyde O-)