Path: utzoo!attcan!uunet!aplcen!haven!adm!smoke!gwyn
From: gwyn@smoke.BRL.MIL (Doug Gwyn)
Newsgroups: comp.sys.apple2
Subject: Re: RISC Machines
Message-ID: <13969@smoke.BRL.MIL>
Date: 30 Sep 90 01:59:18 GMT
References: <8139.apple.net@pro-angmar> <13963@smoke.BRL.MIL> <8971@ucrmath.ucr.edu>
Organization: U.S. Army Ballistic Research Laboratory, APG, MD.
Lines: 24

In article <8971@ucrmath.ucr.edu> rhyde@ucrmath.ucr.edu (randy hyde) writes:
>>>> its opcodes follow no regular pattern...
>Oh yes they do!  It may not appear regular to the unaided eye, ...

The point is, RISC architectures are designed specifically to facilitate
compiler code generation.  There is no way you can convince me that the
6502 meets that requirement; it lacks "orthogonality" in its opcode design.

>At the time the 6501 (yes, "1") was developed, ...

This history is bogus.  I used to program 6800s etc. and the 6502 is close
to a "knock-off" of the 6800 architecturally.

>In this respect, I guess you could all the 6502 a "RISC" chip.

No, the term "RISC" has more specific meaning than simply "puny", as I
remarked previously.

>At the time, the 6502, indeed, was considered the most CISC-like architecture
>around.

At the time, the labels "RISC" and "CISC" were not yet introduced.
When the distinction started being commonly made, the most usual
examples of CISC were the VAX-11 and MC68000 architectures.