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From: gwyn@smoke.BRL.MIL (Doug Gwyn)
Newsgroups: comp.sys.apple2
Subject: Re: RISC Machines
Message-ID: <13981@smoke.BRL.MIL>
Date: 1 Oct 90 02:28:05 GMT
References: <8971@ucrmath.ucr.edu> <13969@smoke.BRL.MIL> <8977@ucrmath.ucr.edu>
Organization: U.S. Army Ballistic Research Laboratory, APG, MD.
Lines: 26

In article <8977@ucrmath.ucr.edu> rhyde@ucrmath.ucr.edu (randy hyde) writes:
>No, back then "similar to the PDP-11" was what people used when they wanted
>to describe what we call a CISC chip today.  The 6800 and 6502 were definitely
>referred to as "PDP-11 like" as opposed to the 8080 which most people called
>brain-dead.

The 68000, not 6800, was PDP-11 like.  The PDP-11, one of the all-time
great computer architectures, was a "general register" machine with
orthogonal addressing modes.  One of its innovations was that general
register # 7 was used as the PC and general register # 6 was used as
the SP; thus the generic address modes available for all registers
were also useful for manipulating PC and SP (although there were some
special PC-only instructions too).  In contrast, the DG Nova, 6800,
6502, PDP-8, DDP-516, CDC 1700, and other minis/micros of the same era
were all "accumulator" machines.  The one exception I know of was TI's
990, which used "register windows" in memory, a slick idea that is near
what some RISC architectures now do.  Certainly none of those CPUs
should be thought of as "RISC"; the current thread of RISC evolution
began with research at UCB and elsewhere and the first commercial RISC
system in this thread was probably Pyramid's.  It certainly is part of
the whole package of ideas known as "RISC" that one will program them
in a higher-level language, not assembler, and the architecture must
therefore be designed with compiler code generation foremost in mind.
Contrast this with virtually all CISC designs, such as VAX and
particularly the 6502, where it is obvious that the instruction-set
architect assumed that one would be programming largely in assembler.