Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cs.utexas.edu!sdd.hp.com!mips!bridge2!jarthur!nntp-server.caltech.edu!tybalt.caltech.edu!toddpw From: toddpw@tybalt.caltech.edu (Todd P. Whitesel) Newsgroups: comp.sys.apple2 Subject: Re: RISC Machines Message-ID: <1990Oct2.083606.8401@nntp-server.caltech.edu> Date: 2 Oct 90 08:36:06 GMT References: <8139.apple.net@pro-angmar> <37682@eerie.acsu.Buffalo.EDU> Sender: news@nntp-server.caltech.edu Organization: California Institute of Technology, Pasadena Lines: 20 Nntp-Posting-Host: tybalt.caltech.edu cromwell@acsu.buffalo.edu (mark j cromwell) writes: >In article <8139.apple.net@pro-angmar> m.tiernan@pro-angmar.UUCP (Michael Tiernan) writes: >>In-Reply-To: message from herwin@pro-novapple.cts.com > The 65x02 aren't RISC processors. They're accumulator microprocessors. This is a fine point. 65x02's have many features that are commonplace on RISC CPUs of today, such as a load/store architecture and fast, simple instructions. They also use an elementary form of pipelining but that is not exploited as much as it could be. However modern RISC CPUs have a lot of features that the 65x02 do not have, such as wide data busses and lots of registers. My favorite quote on the issue is "the 6502 tried to be a RISC before we knew what RISC meant." Todd Whitesel toddpw @ tybalt.caltech.edu