Path: utzoo!attcan!uunet!wuarchive!zaphod.mps.ohio-state.edu!sdd.hp.com!ucsd!ucrmath!berra!rhyde From: rhyde@berra.ucr.edu (randy hyde) Newsgroups: comp.sys.apple2 Subject: Re: RISC Machines Message-ID: <9011@ucrmath.ucr.edu> Date: 2 Oct 90 19:09:11 GMT References: <8139.apple.net@pro-angmar> <37682@eerie.acsu.Buffalo.EDU> <1990Oct2.083606.8401@nntp-server.caltech.edu> Sender: news@ucrmath.ucr.edu Reply-To: rhyde@berra.ucr.edu (randy hyde) Lines: 12 >>> The 6502 tried to be a RISC before we knew what RISC meant... Actually, the 6502 was trying to be a CISC before we knew what CISC meant! You're comparing the instruction set of yesterday against todays instruction sets and coming to the conclusion that the 6502 is a reduced instruction set. Actually, they did reduce the number of instructions over its contemporaries, but they did so be increasing the complexity of each instruction (by adding lots of addressing modes). BTW, the 6502 is *NOT* a load/store architecture. Load/store architectures only give the move instructions (loads and stores) access to memory. The 6502 was fairly generous about letting most applicable instructions access memory.