Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!munnari.oz.au!mel.dit.csiro.au!latcs1!stephens
From: stephens@latcs1.oz.au (Philip J Stephens)
Newsgroups: comp.sys.apple2
Subject: Re: 6502 *IS* RISC (was Re: RISC Machines)
Keywords: RISC, I hate Apple Marketing
Message-ID: <8879@latcs1.oz.au>
Date: 3 Oct 90 03:09:28 GMT
References: <8139.apple.net@pro-angmar> <1990Sep27.025444.11199@ux1.cso.uiuc.edu>
Organization: Comp Sci, La Trobe Uni, Australia
Lines: 24

> >  2.  RISC machines have a large number of general purpose registers. the
> >      6502 doesn't.
> 
>  Uh, actually the 6502 has 256 of them.  They're called "Zero Page Addressing"
>  Access to and from zero page is two cycles- same as an A,X, or Y access.

  Instructions that use zero page addressing are at least 3
cycles in length, where as instructions using register
addressing are only 2.  Even so, you could legitimately call
zero page as a bank of 256 registers, since all indirect
modes (except for the jump instructions) use zero page
variables to store the address in, and access is still
faster than absolute addressing.
  I don't think the 6502 is pipelined, though, since
instructions are executed singly without overlap.  If it
was, I would have noticed the timing discrepancy in my assembly
language programs years ago :-) 

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<  Philip J. Stephens                ><   "Many views yield the truth."        >
<  Hons. student, Computer Science   ><   "Therefore, be not alone."           >
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