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From: toddpw@tybalt.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: 6502 *IS* RISC (was Re: RISC Machines)
Keywords: RISC, I hate Apple Marketing
Message-ID: <1990Oct3.073947.7038@nntp-server.caltech.edu>
Date: 3 Oct 90 07:39:47 GMT
References: <8139.apple.net@pro-angmar> <1990Sep27.025444.11199@ux1.cso.uiuc.edu> <8879@latcs1.oz.au>
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stephens@latcs1.oz.au (Philip J Stephens) writes:

>> >  2.  RISC machines have a large number of general purpose registers. the
>  I don't think the 6502 is pipelined, though, since
>instructions are executed singly without overlap.  If it
>was, I would have noticed the timing discrepancy in my assembly
>language programs years ago :-) 

The 6502 _IS_ pipelined, but in ways that are not very dramatic or even obvious
unless you look at the CPU's internal operation in detail. Rockwell touted the
pipelining in their 6502 user's guide years ago, it is essentially this:

When you do a ADC of something, the last cycle of the instruction is when the
actual data byte is read in, right? Immediately after that the next opcode is
read so the next instruction has started, right? So when did the 6502 add?

It added while the next opcode was being read. The accumulator does not
actually hold the new value until sometime during the second half (forget
exactly where) of the opcode cycle of the next instruction.

That's pipelining. It saves you a cycle on every instruction that does an ALU
operation. It may not be as spectacular as what's being done on the monster
RISCs these days but it is essentially pipelining.

Todd Whitesel
toddpw @ tybalt.caltech.edu