Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cs.utexas.edu!sdd.hp.com!decwrl!petunia!news From: araftis@polyslo.CalPoly.EDU (Alex Raftis) Newsgroups: comp.sys.apple2 Subject: Re: 6502 *IS* RISC (was Re: RISC Machines) Keywords: RISC, I hate Apple Marketing Message-ID: <2709a171.27cb@petunia.CalPoly.EDU> Date: 3 Oct 90 08:29:37 GMT References: <8139.apple.net@pro-angmar> <1990Sep27.025444.11199@ux1.cso.uiuc.edu> <8879@latcs1.oz.au> Organization: Cal Poly State Univ,CSC Dept,San Luis Obispo,CA 93407 Lines: 54 In article <8879@latcs1.oz.au> stephens@latcs1.oz.au (Philip J Stephens) writes: >> > 2. RISC machines have a large number of general purpose registers. the >> > 6502 doesn't. >> >> Uh, actually the 6502 has 256 of them. They're called "Zero Page Addressing" >> Access to and from zero page is two cycles- same as an A,X, or Y access. > > Instructions that use zero page addressing are at least 3 >cycles in length, where as instructions using register >addressing are only 2. Even so, you could legitimately call >zero page as a bank of 256 registers, since all indirect >modes (except for the jump instructions) use zero page >variables to store the address in, and access is still >faster than absolute addressing. > I don't think the 6502 is pipelined, though, since >instructions are executed singly without overlap. If it >was, I would have noticed the timing discrepancy in my assembly >language programs years ago :-) > Your right, a load/store with lda $6/sta $6 would take a 6502 6 cycles. It'd take 4 to do a move d0,d1 on a 68000. So yes, it's slower, but you get 256 byes rather than 8 words to work with. You'd also have to add a cycle to move a full word on a 65816 and a full 12 cycles on a 6502. As for pipelining, the 6502 definitly uses it. Here's an example from "Pro- gramming the 65816" by David Eyes: Step #1: Fetch instruction opcode ADC Step #2: Interpret the opcode to be ADC of a constant Step #3: Fetch the operand, the constant to be added Step #4: Add the constant to the accumulator contents Step #5: Store the result back to the accumulator The pipliningg of the 6502 allows the chip to do steps 2+3 at the same time by incrementing the PC and getting the constant while it interprets the opcode. Then step 4+5 are made to overlap step #1 of the next opcode, thus making the ADC #$xx work in only 2 cycles. True, this isn't true risk which might be able to do it in less time, but it definitly beats out the 68000 which only runs a simple queue. As a point, the 68000 would take 8 cycles to do an ADDI #$xx,D0 (add xx and put in register D0), six more cycles than the 6502. -- -------------------------------------------------- Internet: araftis@polyslo.CalPoly.EDU America Online: xela (Real Life: Alex Raftis)