Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!aplcen!haven!adm!smoke!gwyn
From: gwyn@smoke.BRL.MIL (Doug Gwyn)
Newsgroups: comp.sys.apple2
Subject: Re: RISC Machines
Message-ID: <14009@smoke.BRL.MIL>
Date: 4 Oct 90 08:24:54 GMT
References: <0093D934263990A0.00000110@dcs.simpact.com> <1990Oct2.155706.16241@mintaka.lcs.mit.edu> <14007@smoke.BRL.MIL>
Organization: U.S. Army Ballistic Research Laboratory, APG, MD.
Lines: 29

In article <14007@smoke.BRL.MIL> gwyn@smoke.BRL.MIL (Doug Gwyn) writes:
>However, you are "comparing apples and oranges".  In fact, C compilers
>for the 6502 are not going to generate the sequence that you exhibit.

Indeed, here is the output for the 65816 from APW C:
         stz   $EE                      ;i = 0;
         bra   L0011
L000F    inc   $EE                      ;++i;
L0011    lda   $EE
         sec
         sbc   #$0064
         bvs   L001C
         eor   #$8000
L001C    bpl   L000F                    ;if ( i < 100 ) continue;

And from ORCA/C:
         lda   #$0000
         sta   $07                      ;i = 0;
L01000D  lda   $07
         bmi   L010016
L010011  cmp   #$0064
         bcs   L01001A                  ;if ( !(i < 100) ) break;
L010016  inc   $07                      ;++i;
         bra   L01000D                  ;continue;
L01001A  ...

Note that these are no improvement over the code on a RISC machine.
(In all cases I omitted the function entry/exit code, used to allocate
space for autos on the stack, set the DBR for ORCA/C code, etc.)