Path: utzoo!attcan!uunet!world!esegue!Postmaster
From: johnl@esegue.segue.boston.ma.us (John R. Levine)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: Faster 387s and 486 timing (was: Cyrix CX-803D87-20 Coprocessor)
Message-ID: <9010012252.AA06030@esegue.segue.boston.ma.us>
Date: 2 Oct 90 02:52:47 GMT
References: <14244@shlump.nac.dec.com> <1990Aug4.220844.7349@water.waterloo.edu> <128@thor.UUCP> <1990Sep27.060417.23408@agate.berkeley.edu> <1969@sixhub.UUCP>
Sender: Postmaster@esegue.segue.boston.ma.us
Organization: Segue Software, Cambridge MA
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In-Reply-To: <1990Oct1.163030.3394@maytag.waterloo.edu>

In article <1990Oct1.163030.3394@maytag.waterloo.edu> you write:
>A somewhat related question:  the 486 manuals I've got (which were the source
>for the above) have a column called "Concurrent Execution" in the table
>giving instruction timings, but only for the floating point instructions,
>and as far as I can tell, it's mentioned nowhere in the text.

A careful inspection of the table of contents reveals section 18.2 which is
named CONCURRENT PROCESSING.  It tells us that the internal architecture of
the 486 is similar to a 386/387 combo in that the integer and floating point
units can operate independently.  For example, although the FSIN instruction
takes about 241 cycles, the concurrent time is 2 cycles, so the CPU can
proceed with another integer instruction two cycles later and can execute up
to 239 cycles of fixed point instructions while the FPU thinks.

This is an extreme example since FSIN has to do a lot of work and all of its
sources and results live inside the FPU.  More typical is FMUL which takes
16 cycles with 13 concurrent.  A clever code scheduler (or assembler
programmer) can improve performance quite a lot by interleaving floating and
fixed instructions to keep both units active.

Regards,
John Levine, johnl@esegue.segue.boston.ma.us, {spdcc|ima|world}!esegue!johnl