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From: craig@netcom.UUCP (Craig Hansen)
Newsgroups: comp.sys.mips
Subject: Re: R2000/R2010 instruction set query
Message-ID: <14073@netcom.UUCP>
Date: 29 Sep 90 02:01:45 GMT
References: <3774.27031c0e@cc.curtin.edu.au> <41798@mips.mips.COM> <27202@boulder.Colorado.EDU>
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There is no difference between the R2000/R2010 and the R3000/R3010
in instruction set and latency of operations (in cycles).
The peak execution rate of floating-point adds in either chip
set is 1/2 of the processor clock rate: a floating-point add
has 2 cycles of latency. In fact, if you are very careful,
you can intermix single-precision floating-point multiplies
and adds and maintain that same rate: 2 FP ops in 4 cycles.
15 MFLOPS is achieveable for a 30 MHz machine.
The chips only differ in their pin-out, maximum cache size,
and memory interface features. Perhaps you were talking about
a benchmark that took cache misses...

Regards,
Craig Hansen
craig@microunity.com