Path: utzoo!attcan!uunet!cs.utexas.edu!uwm.edu!zaphod.mps.ohio-state.edu!mips!hal!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.sys.mips
Subject: Re: R2000/R2010 instruction set query
Message-ID: <41860@mips.mips.COM>
Date: 2 Oct 90 13:27:24 GMT
Sender: news@mips.COM
Reply-To: mark@mips.COM (Mark G. Johnson)
Lines: 24

In article <27355@boulder.Colorado.EDU> grunwald@foobar.colorado.edu writes:
>
>what *does* differ between the r2000/r3000? TLB size? write buffer depth?
>
   A subset of the differences [doing this from home :-( so there are more...]
      (1) clock rate: if r3000 then MHz > 16.7
      (2) Block Refill: upon Icache miss, transfer ni (>=1) words from main
                        memory to Icache in a block ... "block refill".  Upon
                        Dcache miss transfer nd words between Dcache and main
                        memory.  ni and nd independently settable at bootstrap
                        time.  R3000 has this, R2000 does not.
      (3) Streaming: When a block refill is occuring, don't stall the machine
                     waiting until the last word in the block is transfered. As
                     soon as the word arrives that you wanted, restart the
                     machine.  As the remaining words in the block whizz by, on
                     their way to the cache, tap them as needed into the CPU
                     (avoids installing a 2nd port on the caches).  R3000 only.
      (4) Internal electrical details that support higher clock rates for r3k
                   such as larger number of VDD/GND bondpads and bondwires,
                   additional on-chip metallization, etc.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}