Path: utzoo!attcan!uunet!mcsun!ukc!axion!garland!jim
From: jim@garland.UUCP (Jim Darby)
Newsgroups: comp.arch
Subject: Re: Looking for a really odd computer
Message-ID: <818@garland.UUCP>
Date: 5 Oct 90 09:03:14 GMT
References: <2721@crdos1.crd.ge.COM> <11791@pucc.Princeton.EDU>
Reply-To: jim@garland.bt.co.uk (Jim Darby)
Organization: RT4253, British Telecom Research Labs, Martlesham Heath, Suffolk.
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In article <11791@pucc.Princeton.EDU> EGNILGES@pucc.Princeton.EDU writes:

>On page 27 of Andrew S. Tanenbaum's book STRUCTURED COMPUTER ORGANIZA-
>TION (Prentice-Hall 1976), there is a list of computers that have
>been sold commercially and their word size.  All are even numbers
>save for one.  This is the "Electrologica X8", with "27 bits per cell."
>I have never heard anything else about this machine, which sounds
>like a vacuum cleaner.

Oh ye modern hackers! <Yorkshire accent on> Back the good old days I used to
use an Elliott 803B. This fine beast had a 39 bit word, and up to 8K words.
Now, you're wondering `How did this work then?'. Well, I'll tell you....

The words could either be considered as a 39 bit word for numerical stuff
(boring) or as *two* instructions. `But how do you split up 39 bits into two?'
you cry. Well, barf bags out at this point, it worked as follows:

+----------+------------------------+-+----------+------------------------+
|   F1     |         ADDR 1         |B|   F 2    |          ADDR 2        |
| 6 bits   |        13 bits         | | 6 bits   |         13 bits        |
+----------+------------------------+-+----------+------------------------+

So, we have two instructions (F1 and F2 (F = function)), and two operand
addresses (ADDR 1 and ADDR 2). This meant that the PC had a notional half value
when executing the second (F2) instruction. Because there wasn't a half bit on
the PC there were two versions of all jumps, one to jump to the first
instruction and another to jump to the second. All rather silly, but not too
grotesque.

BUT WHAT ABOUT THIS MYSTERIOUS `B' THING IN THE MIDDLE? Well, this is where it
gets *fun*. If the `B' bit was clear, then the machine would execute the left
hand then the right hand instruction. However, if the `B' bit was SET, then the
value in the address ADDR 1 would be added to F2 and ADDR 2 *before* F2 with
its ADDR 2 operand were executed, allowing address modification. So, to load
the accumulator indirect through location 100 you would do the following.

        NOP 100 ! LDA 0

The NOP 100 would do nothing with address 100, however the `!' set the `B' bit
so the contents of location 100 would be added to the LDA address. Good eh?

Now, all the hackers amongst you will have noticed that I said that the `B' bit
caused the F2 as well as the ADDR 2 field to be added to. This is all OK if the
modifier was still in the address range, but if you went over 8K words then you
modified the instruction field. This is how the loader worked. I took me ages
to figure out that the way it entered your program was to modify the
instruction that stored the data into a jump to the start of the code! Boffo, a
good one!

Makes the Sparc seem sane, doesn't it?

Jim.