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From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: inequality vs. less-than
Message-ID: <8000@scolex.sco.COM>
Date: 3 Oct 90 21:45:17 GMT
References: <7341@darkstar.ucsc.edu> <1990Sep30.050655.13212@zoo.toronto.edu> <1990Sep30.172917.2951@Neon.Stanford.EDU> <DAVIS.90Oct1025438@pacific.mps.ohio-state.edu> <1990Oct2.151644.1581@phri.nyu.edu> <469@kaos.MATH.UCLA.EDU>
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In article <469@kaos.MATH.UCLA.EDU> pmontgom@euphemia.math.ucla.edu (Peter Montgomery) writes:
>	On the now obsolete CDC Cyber systems (ones complement)
>the compare and branch were combined into one instruction.  
>Let Xi denote a 60-bit register.  The major branch instructions were
>
>		ZR Xi,address		Branch if Xi == 0 (+0 or -0)
>		NZ Xi,address		Branch if Xi != 0 (neither +0 nor -0)
>		PL Xi,address		Branch if Xi >= 0 (look at sign bit)
>		MI Xi,address		Branch if Xi <  0 (look at sign bit)
>		(four others tested out of range floating point values)

On the other hand, if the compiler could restrict the values to 18 bits,
then it could use

	EQ r1,r2,addr
	NE r1,r2,addr
	GT r1,r2,addr
	GE r1,r2,addr
	LT r1,r2,addr
	LE r1,r2,addr

where r1 and r1 are one of the A or B registers.  Note that since B0 was a
hardwired 0, you also got ZR, NZ, PL, and MI thrown in for free.

The FORTRAN compiler would normally use the B registers for looping and
indexing; this allowed normal loops to have all the conditionals normally
expected.

-- 
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