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From: holmer@ernie.Berkeley.EDU (Bruce K. Holmer)
Newsgroups: comp.arch,comp.lsi.cad
Subject: Opcode assignment for RISC processors
Message-ID: <39029@ucbvax.BERKELEY.EDU>
Date: 5 Oct 90 18:11:41 GMT
Sender: usenet@ucbvax.BERKELEY.EDU
Reply-To: holmer@ernie.Berkeley.EDU (Bruce K. Holmer)
Organization: University of California, Berkeley
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*

I'm curious how the architects for new RISC processors come up with
the opcode assignments (i.e. which bit pattern goes with which
instruction).

I know about the tools for state assignment of finite state machines,
but opcode assignment is a slightly different problem.  The need to
come up with an opcode assignment is a relatively rare occurrence
(since it is done only once for each processor family), so I wouldn't
think people would invest much time in writing a fancy tool for it.

Our research group has designed a 32-bit RISC and I'm in the process
of writing up a short report on how I did the opcode assignment.  We
had some unusual constraints on some of the opcodes, which made the
problem less than straight forward.  I used a simple form of simulated
annealing that is very easy to code from scratch (it took two days
from the initial idea to the final result--that includes time for
writing the code and running it many times).  The results were
satisfactory--the number of minterms in the decode PLAs reduced on
average about 20%.

But perhaps the problem is even easier than I think, so I'd be curious
what others have done (especial curious about the commercial
processors--MIPS, SPARC, 29000, etc.).

If you would like a copy of my report, send me email--but it will be a
couple of weeks before I have something to mail.

Thanks,
Bruce Holmer
holmer@ernie.berkeley.edu