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From: peter@ficc.ferranti.com (Peter da Silva)
Newsgroups: comp.arch
Subject: Re: Opcode assignment for RISC processors
Message-ID: <-S86F-8@xds13.ferranti.com>
Date: 7 Oct 90 01:46:30 GMT
References: <39029@ucbvax.BERKELEY.EDU> <4153@bingvaxu.cc.binghamton.edu> <41963@mips.mips.COM>
Reply-To: peter@ficc.ferranti.com (Peter da Silva)
Organization: Xenix Support, FICC
Lines: 9

In article <41963@mips.mips.COM> mash@mips.com (John Mashey) writes:
> The SPECIAL opcode and SLL sub-opcode were selected
> to be zero, so that a 32-bit zero would produce a NOP.
> I would consider this to be of esthetic value only.

As a long-time embedded systems hacker, I'd recommend that on any
machine 00000000 and FFFFFFFF both be illegal instructions, or
otherwise cause a trap. This makes software crash quickly instead
of slowly when it goes out in the weeds.
-- 
Peter da Silva.   `-_-'
+1 713 274 5180.   'U`
peter@ferranti.com