Path: utzoo!attcan!uunet!decwrl!wuarchive!zaphod.mps.ohio-state.edu!lavaca.uh.edu!menudo.uh.edu!sugar!ficc!peter From: peter@ficc.ferranti.com (Peter da Silva) Newsgroups: comp.arch Subject: Re: Opcode assignment for RISC processors Message-ID: Date: 8 Oct 90 15:59:10 GMT References: <39029@ucbvax.BERKELEY.EDU> <4153@bingvaxu.cc.binghamton.edu> <41963@mips.mips.COM> <-S86F-8@xds13.ferranti.com> Reply-To: peter@ficc.ferranti.com (Peter da Silva) Organization: Xenix Support, FICC Lines: 9 In article meissner@osf.org (Michael Meissner) writes: > Data General Nova's, Eclipse's, and MV/Eclipse's were particularly bad > in this respect. A full 16-bit 0 was a jump to location 0 (in the > current ring/segment on MV/Eclipse). ... #define URBAN_LEGEND maybe: In one of the TI minis, 0 tuned out to be "store immediate 0". Executing 0 would fill memory with 0 as fast as the PC could increment. -- Peter da Silva. `-_-' +1 713 274 5180. 'U` peter@ferranti.com