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From: sb380@cs.city.ac.uk (Andy Holt)
Newsgroups: comp.arch
Subject: Re: Opcode assignment for RISC processors
Message-ID: <1990Oct8.111536.11084@cs.city.ac.uk>
Date: 8 Oct 90 11:15:36 GMT
References: <39029@ucbvax.BERKELEY.EDU> <4153@bingvaxu.cc.binghamton.edu> <41963@mips.mips.COM>
Reply-To: sb380@city.ac.uk (Andy Holt)
Organization: City University, London
Lines: 16

In article <41963@mips.mips.COM> Craig Hansen passes along the following:
> ....
>The SPECIAL opcode and SLL sub-opcode were selected
>to be zero, so that a 32-bit zero would produce a NOP.
>I would consider this to be of esthetic value only.
>
> ....
There seem to be two popular choices for the effect of an all-zero
opcode. Craig's choice of NOP has aesthetic appeal, and has been 
used by many systems. But IMO a much better choice is to make it
some form of trap or illegal opcode (cf HLT on PDP11) thus improving
considerably on the chances of catching overwriting problems.
(OK, OK, modern systems normally have write protected code segments,
but ...)

Andy