Path: utzoo!utgpu!cunews!bnrgate!bigsur!bnr-rsc!bcarh185!schow
From: schow@bcarh185.bnr.ca (Stanley T.H. Chow)
Newsgroups: comp.arch
Subject: Re: speculative execution
Message-ID: <3432@bnr-rsc.UUCP>
Date: 10 Oct 90 04:05:59 GMT
References: <1990Oct9.162639.23516@rice.edu> <3431@bnr-rsc.UUCP> <1990Oct9.224312.2031@rice.edu>
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Reply-To: bcarh185!schow@bnr-rsc.UUCP (Stanley T.H. Chow)
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In article <1990Oct9.224312.2031@rice.edu> preston@titan.rice.edu (Preston Briggs) writes:
>In article <3431@bnr-rsc.UUCP> bcarh185!schow@bnr-rsc.UUCP (Stanley T.H. Chow) writes:
>>Hmm, you mean your compiler can schedule code so that five instructions
>>are issued to one function unit on every clock?
>>There are some occasions when multiple copies of h/w can do better than
>>compiler. I believe speculative execution is one.
>
>Given the same number of functional units, with same latencies,
>same number of registers, ...
>I believe I can write a compiler that will make code run
>faster than hardware that does speculative execution.
>My version of the hardware should also be cheaper
>in that it doesn't have to coordinate the multiple paths of speculation.

I assume you mean given two machines, otherwise identical, differing
only in that M1 does hardware speculative execution and M2 does not,
you can write a compiler that will make M2 run faster than M1.

This sounds wrong. I do not doubt that you can speedup M2 by speculative
execution (with hoisting, etc). But surely the same technology can be
applied to M1 with the same result. A priori, I would expect the benifit
to be the same for both machines.

On the other hand, there are many things that *need* H/W. E.g., pre-
fetching (and executing) multiple paths. Surely these gains are additive
to those of the compiler.

(This is not to say that H/W speculative execution is easy or even
possible, and certainly says nothing about the relative gains or the
relative difficulty of H/W vs S/W).

Stanley Chow        BitNet:  schow@BNR.CA
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