Path: utzoo!attcan!uunet!mcsun!i2unix!inria!irisa!priol
From: priol@irisa.fr (Thierry Priol)
Newsgroups: comp.arch
Subject: Re: Shared Memory
Message-ID: <1990Oct9.174307.27365@irisa.fr>
Date: 9 Oct 90 17:43:07 GMT
References: <10678@pt.cs.cmu.edu>
Sender: news@irisa.fr
Organization: IRISA, Rennes (FR)
Lines: 31

A software user point of view in using a Shared Virtual Memory on
Distributed Memory Parallel Computer.

We have recently worked on implementing a SVM on an iPSC/2. Using
a SVM on DMPC can improve the efficiency of some irregular algorithms
(Ray-tracing, LocusRoute, Metal, etc...). We have tested a message-based
and shared-memory approach on our iPSC/2. Results are better with the
second approach!

Several works has been done recently to design a hardware device
for implementing efficiently a SVM (PLUS from CMU, ALEWIFE from MIT,
Kendall Square Research, and some European Esprit Projects). These
parallel computers are scalable and provide a shared memory. Cache
coherence is a difficult problem (not solved on BBN (no cache) or RP3
(cache but not coherence by hardware (software only), i think?).
There are some ideas for managing cache coherence by analyzing programs
which allow to minimize the cost of cache coherence (A. Veidenbaum paper
or Cytron and al.)

may be, these new architectures are the next generation of DMPC ?

What are your feeling about that ?


NB : i apologize for my poor english.

-- 
Thierry PRIOL                                Phone:  99 36 20 00
IRISA / INRIA U.R. Rennes                    Fax:    99 38 38 32
Campus Universitaire de Beaulieu             Telex:  UNIRISA 950 473F
35042 RENNES CEDEX - FRANCE                  E-mail: priol@irisa.fr