Path: utzoo!attcan!uunet!jarthur!usc!samsung!dali.cs.montana.edu!uakari.primate.wisc.edu!sdd.hp.com!hplabs!hpcc05!hpcuhb!hpcllla!hpclisp!hpclscu!shankar
From: shankar@hpclscu.HP.COM (Shankar Unni)
Newsgroups: comp.arch
Subject: Re: Opcode assignment for RISC processors
Message-ID: <650015@hpclscu.HP.COM>
Date: 9 Oct 90 19:57:48 GMT
References: <39029@ucbvax.BERKELEY.EDU>
Organization: Hewlett-Packard Calif. Language Lab
Lines: 15

> / hpclscu:comp.arch / peter@ficc.ferranti.com (Peter da Silva) /  6:46 pm  Oct  6, 1990 /
> In article <41963@mips.mips.COM> mash@mips.com (John Mashey) writes:
> > The SPECIAL opcode and SLL sub-opcode were selected
> > to be zero, so that a 32-bit zero would produce a NOP.
> > I would consider this to be of esthetic value only.
> 
> As a long-time embedded systems hacker, I'd recommend that on any
> machine 00000000 and FFFFFFFF both be illegal instructions, or
> otherwise cause a trap. This makes software crash quickly instead
> of slowly when it goes out in the weeds.

Absolutely. In HP's Precision Architecture (sorry, PA-RISC ..), 0 decodes
to "BREAK 0,0", which raises a break trap.
---
Shankar Unni.