Path: utzoo!utgpu!cunews!bnrgate!bigsur!bnr-rsc!bcarh185!schow
From: schow@bcarh185.bnr.ca (Stanley T.H. Chow)
Newsgroups: comp.arch
Subject: Re: speculative execution
Message-ID: <3435@bnr-rsc.UUCP>
Date: 10 Oct 90 19:55:13 GMT
References: <1990Oct9.212103.363@rice.edu> <12905@encore.Encore.COM>
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Reply-To: bcarh185!schow@bnr-rsc.UUCP (Stanley T.H. Chow)
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In article <12905@encore.Encore.COM> jkenton@pinocchio.encore.com (Jeff Kenton) writes:
>From article <1990Oct9.212103.363@rice.edu>, by preston@titan.rice.edu (Preston Briggs):
>> 
>> In general, we need to be careful about fatally increasing
>> register pressure.  The i860's exposed pipeline provides an
>> elegant way out, allowing simple aborts of optimistic 
>> computations by ignoring what's partially computed in
>> the pipe.
>> 
>
>It would take a lot to convince me that the i860 is an elegant solution
>to anything.  No one has produced a compiler which can take advantage of
>the theoretically possible parallelism of the i860.  It's a very fast
>chip for certain kinds of applications, but I wouldn't call it elegant,
>or general purpose.

In the context of this discussion - Speculative Execution, exposing the
pipeline AND letting S/W control the flow of oeprand/result through it
makes sense. As Preston Briggs points out, it is easy (on the i860) to
start execution, there is no cost in terms of register usage or issuing
instructions. Other current micros will tie up the result register 
and/or require a seperate instruction issue slot.

Anyway, wasn't the i860 designed as a numeric coprocessor? I think of
it as DSP-like but with enough "General Purpose" that it does not need
a "controller".

Stanley Chow        BitNet:  schow@BNR.CA
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