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From: gillies@m.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: speculative execution
Message-ID: <3300194@m.cs.uiuc.edu>
Date: 11 Oct 90 02:51:00 GMT
References: <162639@<1990Oct9>
Lines: 30
Nf-ID: #R:<1990Oct9:162639:m.cs.uiuc.edu:3300194:000:1405
Nf-From: m.cs.uiuc.edu!gillies    Oct 10 21:51:00 1990


> No one has produced a compiler which can take advantage of the
> theoretically possible parallelism of the i860.  It's a very fast chip
> for certain kinds of applications, but I wouldn't call it elegant, or
> general purpose.

One of the problems in new CPU designs is that designers don't realize
which architecture enhancements are pointless, because we don't and
may never have the optimization technology to take advantage of them.

Many enhancements to "increase parallelism" cannot be exploited by
compilers unless P = NP, or unless you are willing to wait {hours,
days, weeks} for your compiler to finish its job.  So don't just
relegate EVERYTHING to the compiler!

When you do something like add dedicated functional units to a CPU,
you are (potentially) increasing the complexity of the scheduling from
say, triangle-inequality traveling salesman (for which a heuristic
with bounded performance exists), to full generality traveling
salesman (for which no bounded heuristic exists unless P = NP).

I believe you are much better off spending the extra real estate to
implement identical functional units, or add vector hardware, since
the compiler technology for exploiting these features runs in
polynomial time.


Don W. Gillies, Dept. of Computer Science, University of Illinois
1304 W. Springfield, Urbana, Ill 61801      
ARPA: gillies@cs.uiuc.edu   UUCP: {uunet,harvard}!uiucdcs!gillies