Path: utzoo!attcan!uunet!mcsun!hp4nl!charon!dik From: dik@cwi.nl (Dik T. Winter) Newsgroups: comp.arch Subject: Re: speculative execution Message-ID: <2321@charon.cwi.nl> Date: 11 Oct 90 15:22:56 GMT References: <12905@encore.Encore.COM> <1990Oct10.164353.21070@rice.edu> Sender: news@cwi.nl Organization: CWI, Amsterdam Lines: 43 In article philip@beeblebrox.dle.dg.com (Philip Gladstone) writes: > In article <1990Oct10.164353.21070@rice.edu> preston@titan.rice.edu (Preston Briggs) writes: > [stuff deleted] [more stuff deleted] > > int-1, pfmul.ss f3,f4,f0 <--- These floats hoisted from > > int-2, pfmul.ss f0,f0,f0 <--- from the if > > int-3, pfmul.ss f0,f0,f0 > > if (something) { > > pfmul.ss f0,f0,f5 > > } > > fst.l f5,somewhere > > The true path get much shorter. > > No increase in the path length of the false path. > > And no extra register required. > It seems to me that it is very difficult to spot when this is legal or not. > It is assumed in this example that none of the hoisted instructions > will cause any problems if they are executed when the programmer did > not intend them to be executed. This raises a point, although for different reasons. I wil start with some explanations: on the i860, if (for instance) a floating-point instruction overflows, a status bit is set and if this status bit is set the next floating-point instruction will trap. If we assume the pipeline was empty when this sequence started the hoisted instructions will not set status bits and do not deliver a result. It is only the last (conditional) instruction that can set a status bit and deliver a result; but that instruction does not take any source operands. So in this aspect the example is valid. There is another aspect: after the three pfmul instructions the pipeline is filled in an indeterminate state if the false path is to be taken. There might be an overflow status or somesuch pending in the last stage, and that must be cleared. The only ways I see to clear this is either to perform a non pipelined multiply after such a sequence (which voids the pipeline) or else you need in the false path an instruction to drain the pipeline (pfmul.ss f0,f0,f0) and an instruction to clear status bits in the fsr. As far as I see, in both cases you will lose in some cases what you gain in others. And yes, the Alliant compiler generates pipelined instructions and dual instruction mode instructions. -- dik t. winter, cwi, amsterdam, nederland dik@cwi.nl