Path: utzoo!attcan!uunet!convex!swarren From: swarren@convex.com (Steve Warren) Newsgroups: comp.sys.amiga Subject: Re: Amiga Competitiveness. Message-ID: <106691@convex.convex.com> Date: 30 Sep 90 00:27:19 GMT References: <1990Sep27.203058.601@sisd.kodak.com> Sender: usenet@convex.com Organization: Convex Computer Corporation, Richardson, Tx. Lines: 82 In article peck@ral.rpi.edu (Joseph Peck) writes: [...] >the 2000 is supposed to be for "serious" work). Now, since the accelerator >boards only advantage (aside from the better processor) is the memory, There are three major advantages to buying a coprocessor with memory: 1) Improved performance of the processor - it doesn't require as many cycles for the improved processor as it takes on a standard 68000. 2) Faster clock speed - the newer processor can run on a faster clock, so the cycles themselves are shorter. 3) The data bus between the coprocessor and the memory card is 32 bits wide - this is because the new processor is a 32-bit processor. The memory on these boards may be as much as 30% faster than the memory on a standard A2000, but not much more. The big advantage is in bus-width, which can double performance in many cases. > ... why >can't we use a faster 16 bit memory board? If it can't go in the zorro >slots, can't it use the CPU slot? The faster your memory board is the better your performance will be, until you get to zero wait-states, at which point speeding up your memory doesn't buy you anything. This has nothing to do with the Zorro spec. The 680x0 family uses an "asynchronous" bus, which means that the processor has to wait until the memory it is accessing reports that it is done before the processor can do anything else. This means that there is no such thing as memory that is "too slow", unless you want to get ridiculous and try to force thousands of wait states on a single access. At 14 MHz or approximately 70 ns cycle time, a typical bus cycle of four clocks for the 68000 is 280 ns. Typical cycle time for a 120 ns DRAM with no fancy nibble or static column modes is around 220 ns, including precharge and other requirements. That leaves 60 ns for other delays in the circuit. Using a 100 ns DRAM will buy you about 30 ns more for other delays in your circuit. At 7 MHz you (the designer) basically have "all day" for your circuit's delays. At 25 MHz you're not going to get 100% zero wait states using normal DRAMs. 80 ns DRAMs have a cycle time of 160 ns, which is the same time required for a 68000 bus cycle. Other processors may have a shorter bus cycle. That is why there is a market for fast caches. The designer just inserts wait states in his design which force the processor to wait until the data is ready in the memory. > ... I don't have the technical manuals for >any of the amiga's (RKM manuals are much help here), so I could be way off >base. > >In fact, the more I think about it, doesn't the 2500 come with 100ns memory >chips? If those are fast enough for 25Mhz, shouldn't the 120ns chips in >an 8UP! board be good enough for a 14Mhz 68000? See above; 100 ns is not fast enough for zero wait states at 25 MHz. >Finally, even if it is only a 20% increase, 14Mhz would make a better >marketing point, something that the Amiga needs..... Well, a memory board designed for zero wait states on a 14 MHz Amiga would really give new emphasis to the phrase "fast ram". Your Amiga would run at double speed out of fast ram. But it would still be slow when accessing chip ram. This could actually be a nice little hack. Something like the Lucas project. Many people would be happy with 2X performance, especially if they could switch back to 1X under software control (just set up the memory card with a programmible div-by-2 on the clock). -- _. --Steve ._||__ DISCLAIMER: All opinions are my own. Warren v\ *| ---------------------------------------------- V {uunet,sun}!convex!swarren; swarren@convex.COM