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From: swarren@convex.com (Steve Warren)
Newsgroups: comp.sys.amiga,comp.sys.amiga.hardware
Subject: Re: Bank switched CHIP RAM?  (Re: 24 Bit Video ..)
Keywords: Off the wall idea?
Message-ID: <106878@convex.convex.com>
Date: 5 Oct 90 14:39:58 GMT
References: <1990Sep28.022138.19237@zip.eecs.umich.edu> <1990Sep30.233751.3244@zorch.SF-Bay.ORG> <1990Oct3.194556.7031@lth.se>
Sender: news@convex.com
Followup-To: comp.sys.amiga.hardware
Organization: Convex Computer Corporation, Richardson, Tx.
Lines: 42

In article <1990Oct3.194556.7031@lth.se> d87sg@efd.lth.se (Svante Gellerstam) writes:
                               [...]
>Interlace screen on a A3000. Even on a 25MHz '030 a measly
>(professionally speaking) 640 x 400 screen becomes zippy as old
>chewinggum. 
                               [...]
The solution to the bandwidth problem is banks.  We already have two
seperate banks of chip mem in the 3000 with 2 Megs of chip.  The trick
is to set it up so that as long as the video DMA is accessing one of the two
banks, the CPU can have transparent access to the other bank simultaneously
(ie no cycle-stealing necessary).  The best way to utilize this is by using
an 8- or 16- byte interleave, so that every 16 consecutive bytes will be
in alternating banks.

The CPU could then write at full speed in a 16-byte space until it ran
into the back end of the next 16 bytes in the other bank (which the video
DMA would be accessing).  Then it would be wait-stated until the video DMA
moved into the first bank again, at which time the CPU could continue
writing at the next locations.  This would give the CPU greater bandwidth to
chip mem at the highest available screen resolution than it currently gets at
the lowest resolution.  This setup would lower chip-mem contention
significantly, probably to the point that it would no longer be noticeable.

This would be fairly simple to implement.  The chip-mem system is already dual
ported.  The dual ports need to be extended into the two banks so that
they may be seperately addressed on the same cycle, and the address mapping
of the 2 banks relative to each other would change.

The bandwidth requirements at 1280 x 1024 are another matter.  Standard DRAMs
can be used for that but you have to go to a tighter interleave or a wider
data bus to the video section.  A wider data bus would probably be the
cheapest solution.  Now that there are 1 Mbit DRAM chips with 16-bit data
busses this solution is not unreasonably expensive.  With four chips you can
get a 512 Kbyte bank with a 64-bit data bus.

Note the follow-up line.

--
            _.
--Steve   ._||__      DISCLAIMER: All opinions are my own.
  Warren   v\ *|     ----------------------------------------------
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