Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!cbmvax!daveh From: daveh@cbmvax.commodore.com (Dave Haynie) Newsgroups: comp.sys.amiga Subject: Re: A4000,Lotus,Microsoft,UNIX... Message-ID: <15004@cbmvax.commodore.com> Date: 9 Oct 90 22:42:51 GMT References: <32040@nigel.ee.udel.edu> <22345@grebyn.com> <2040@jimi.cs.unlv.edu> <14898@cbmvax.commodore.com> <3154@medusa.informatik.uni-erlangen.de> Reply-To: daveh@cbmvax.commodore.com (Dave Haynie) Organization: Commodore, West Chester, PA Lines: 65 In article <3154@medusa.informatik.uni-erlangen.de> csbrod@medusa.informatik.uni-erlangen.de (Claus Brod ) writes: >daveh@cbmvax.commodore.com (Dave Haynie) writes: >>Really? I though they would have some equivalent to Fast memory. Of course, >The TT has its equivalent of Fast mem. OK. I really thought it must; that kind of architecture demands it. >How many waitstates would I get in a A3000 in chip/fast/ultra-fast/whatever >RAM, by the way? First you have to define wait state. In 68030 terms, a 0 wait state bus cycle is either a 2 clock sychronous cycle or a 3 clock asynchronous cycle. But of course a 0 wait state asynchronous cycle is just a fast as a 1 wait state synchronous cycle. Then there's burst mode -- a 0 wait state burst cycle (which can only follow a synchronous cycle or another burst cycle) happens in one clock. And a spec sheet may claim "0 wait state effective speed", but really mean a 5 clock synchronous cycle followed by three 1 clock burst cycles. Which adds up to 8 clocks, same number of clocks as four 0-wait state synchronous cycles, but really isn't as fast, since burst fetched data is thrown out on occasion. So, for built-in Fast memory, you get: Mode 25MHz 16MHz Basic 5 clocks 4 clocks Burst 2 clocks 2 clocks Page Detect 3/7 clocks 3/6 clocks At least, I think those are the right numbers. The "Page Detect" mode is a feature of the custom memory controller. In this mode, the controller locks in the memory page (technically, the row address to the DRAM) in a normal memory cycle, and any cycles following it on that same page happen faster. If a different page is addressed, there's a small penalty taken to close the current page, followed by a normal memory access to open the new page. As for other memory, the CPU slot can support true 0-wait state RAM, if you can find any :-), as well as 0-wait state external cache memory. The best Zorro III bus access in the A3000 implementation is in 5 clocks (for any clock speed), but because of bus overhead, you'll need much faster memory to achieve that performance than you would for CPU slot or motherboard memory. Zorro III burst mode can cut down on the overhead just as 68030 burst does for the 68030 bus. Cycles on the Zorro III bus can actually be faster, between good Zorro III devices, since Zorro III burst can run 64 longwords, vs. the 4 longword burst cycle of the 68030 bus. Chip memory access is probably more like 14-15 clocks at 25MHz or 8-9 clocks at 16MHz, same basic idea with Zorro II memory access (and of course, Zorro II access is also 16 bits wide). You can't tell exactly how fast a given cycle to Zorro II or Chip memory is because there is a bit of clock synchronization, which is different depending on the relative positions of the 16/25MHz clock with respect to the 7MHz clock. >Claus Brod, Am Felsenkeller 2, Things. Take. Time. >D-8772 Marktheidenfeld, West Germany (Piet Hein) >csbrod@medusa.informatik.uni-erlangen.de -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Standing on the shoulders of giants leaves me cold -REM