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From: jms@tardis.Tymnet.COM (Joe Smith)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Bank switched CHIP RAM?  (Re: 24 Bit Video ..)
Summary: CHIP ram is not dual ported.
Message-ID: <1280@tardis.Tymnet.COM>
Date: 10 Oct 90 01:28:57 GMT
References: <1990Sep28.022138.19237@zip.eecs.umich.edu> <1990Sep30.233751.3244@zorch.SF-Bay.ORG> <1990Oct3.194556.7031@lth.se> <106878@convex.convex.com>
Reply-To: jms@tardis.Tymnet.COM (Joe Smith)
Organization: BT Tymnet, San Jose, CA
Lines: 28

In article <106878@convex.convex.com> swarren@convex.com (Steve Warren) writes:
>The solution to the bandwidth problem is banks.  We already have two
>seperate banks of chip mem in the 3000 with 2 Megs of chip.  The trick
>is to set it up so that as long as the video DMA is accessing one of the two
>banks, the CPU can have transparent access to the other bank simultaneously
>(ie no cycle-stealing necessary). This would be fairly simple to implement. 
>The chip-mem system is already dual ported.

One major problem.  The Chip RAM is NOT dual ported.  There is not a set
of address & data lines coming from the CPU and another set from the graphic
chips.  None of the CPU address lines go to the RAM that is Chip memory.
Although the memory system does have seperate RAS and CAS strobes, it has
only a single set of row/column address lines.

All access to Chip RAM go through Agnus.  The "dual porting" is done inside
Agnus.  Requests to access Chip memory can come from the CPU bus or from
Agnus DMA registers.  It is Agnus who decides whether to honor the external
request or an internal one.  Without Agnus' cooperation, the CPU gets nothing.

True dual porting needs RAM chips twice as fast as the current ones, to
ensure that Agnus gets its data on time in all cases (including when the CPU
gets there first).  Remember, these graphics chips cannot tolerate any wait
states whatsoever.
-- 
Joe Smith (408)922-6220 | SMTP: jms@tardis.tymnet.com or jms@gemini.tymnet.com
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