Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!convex!swarren
From: swarren@convex.com (Steve Warren)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Bank switched CHIP RAM?  (Re: 24 Bit Video ..)
Message-ID: <107026@convex.convex.com>
Date: 10 Oct 90 14:08:31 GMT
References: <1990Oct3.194556.7031@lth.se> <106878@convex.convex.com> <1280@tardis.Tymnet.COM>
Sender: usenet@convex.com
Organization: Convex Computer Corporation, Richardson, Tx.
Lines: 59

In article <1280@tardis.Tymnet.COM> jms@tardis.Tymnet.COM (Joe Smith) writes:
>In article <106878@convex.convex.com> swarren@convex.com (Steve Warren) writes:
>>The solution to the bandwidth problem is banks.  We already have two
>>seperate banks of chip mem in the 3000 with 2 Megs of chip.  The trick
>>is to set it up so that as long as the video DMA is accessing one of the two
>>banks, the CPU can have transparent access to the other bank simultaneously
>>(ie no cycle-stealing necessary). This would be fairly simple to implement. 
>>The chip-mem system is already dual ported.
>
>One major problem.  The Chip RAM is NOT dual ported.  There is not a set
>of address & data lines coming from the CPU and another set from the graphic
                                    [...]
You need to reread my post, Joe.  I never said the chip *RAM* was dual-ported.
I said the *chip-mem system* was dual ported.  The chip-mem system obviously
includes Agnus.  I stated in my post that the ports would have to be extended
down into the ram organization by providing seperate switchable ports into
each of the two banks.

>All access to Chip RAM go through Agnus.  The "dual porting" is done inside
>Agnus.  Requests to access Chip memory can come from the CPU bus or from
>Agnus DMA registers.  It is Agnus who decides whether to honor the external
>request or an internal one.  Without Agnus' cooperation, the CPU gets nothing.

Of course.  This is not a problem.

>True dual porting needs RAM chips twice as fast as the current ones, to
>ensure that Agnus gets its data on time in all cases (including when the CPU
>gets there first).  Remember, these graphics chips cannot tolerate any wait
>states whatsoever.

This is not true (that the ram chips have to be twice as fast).  I work in
the development of multi-ported memory systems.  We use interleaved banks
of 100 ns DRAMs.  The memory systems we produce are used in CONVEX
supercomputers.  It is the *system* that has to be faster, not the individual
chips.

By properly designing the controller it is possible to use the 2-bank/2-port
system I described, although I did not go into any details.  You would have to
preemtively lock the processor out of the next bank when the graphics
processor is on the last location in the first bank.  These are details, but
I assure you that it is possible with normal speed drams and to present the
graphics processor with unrestrained access to the chip mem, while providing
the CPU with greatly enhanced bandwidth to the same memory space.  All waits
that were necessary would of course be applied to the CPU, not the graphics
processor.

In any case, I don't think it matters that much, since any decisions of
this nature have most likely already been made for some time.  The solution
I described is quite doable, though.  And not especially more complex than
the system already implemented on the 3000 (but it is a little more complex).
More I/O pins to double the number of dram control/address/data ports would
be required.  Agnus or something new would be required to do the muxing of
the two ports.  Etc.

--
            _.
--Steve   ._||__      DISCLAIMER: All opinions are my own.
  Warren   v\ *|     ----------------------------------------------
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