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From: jb10320@uxa.cso.uiuc.edu (Desdinova)
Newsgroups: comp.sys.apple2
Subject: IIgs memory timing question
Summary: Need timing info to implement virtual memory
Message-ID: <1990Oct9.013212.29147@ux1.cso.uiuc.edu>
Date: 9 Oct 90 01:32:12 GMT
Sender: news@ux1.cso.uiuc.edu (News)
Organization: University of Illinois at Urbana
Lines: 30

Hopefully someone out there can answer this.

After poring through the IIgs hardware reference for a couple hours
today, I realized that it says nothing about the timing of the FPI.
Specifically, what I need to know is how soon after phase2 goes low
(start of the address cycle) does the FPI output the RAS and CAS
signals?  And what is the latency (i.e. how long does it take the FPI
to generate the RAS and CAS?

If I had a 'scope I'd know, but I don't.  And I don't really feel like
hauling my GS to the lab halfway across campus.

I need to know this so I can know how fast I must do a 16 or 24-bit
addition on the 65816's address bus.  I can do a 24-bit compare in
22ns (faster if I want to pay for ECL chips).

What I'm doing is designing a virtual memory system for the GS.
It's a simplistic type, with just a BASE and BOUNDS register.  But
that's enough to do memory protection, and make all processes 
relocatable, and thus implement Unix.

I'm hoping, praying, that somone from Apple still reads this. I
don't really wanna pay long-distance to ask 'em in person.

--
Jawaid Bazyar               | Blondes in big black cars look better wearing
Senior/Computer Engineering | their dark sunglasses at night. (unk. wierdo)
jb10320@uxa.cso.uiuc.edu    |      The gin, the gin, glows in the Dark!
                            |                             (B O'Cult)
Apple II Users Unite! Storm the New Product Announcement and Demand Justice!