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From: brucee@runxtsa.runx.oz.au (Bruce Evans)
Newsgroups: comp.sys.intel
Subject: Re: Zero wait state and caches
Keywords: wait states, cache
Message-ID: <2400@runxtsa.runx.oz.au>
Date: 9 Oct 90 12:15:22 GMT
References: <188@nat-3.UUCP> <1466@svin02.info.win.tue.nl>
Organization: RUNX Unix Timeshare.  Sydney, Australia.
Lines: 23

In article <1466@svin02.info.win.tue.nl> wsinpdb@svin02.info.win.tue.nl (Paul de Bra) writes:
>A cache system provides zero wait states on a cache hit, but one or two
>wait states on a cache miss. Given sufficient cache memory (64k or more)
>the hit rate is fairly close to 100%, and the performance increase is
>substantial.

For cheap 386 cache systems, claiming one or two wait states for cache misses
may be stretching the truth almost as much as claiming zero wait states. I
have a 33 MHz system that claims 2 wait states for a cache miss with a page
hit and 4 wait states for a cache miss without a page hit. A benchmark that
copies the n'th megabyte of physical memory to the m'th megabyte using
"rep movsd" gives times between 0.09 sec (12 cycles per dword = 8 cycles
overhead) and 0.24 sec (32 cycles per dword = 28 cycles overhead) for
different values of m and n in the range 2 to 6. The times are very
sensitive to m and n.

I suspect that the memory off the motherboard has more wait states (though
it is claimed to be 32-bit) and the cache is thrashing due to the non-random
pattern of accesses (reading extra and discarding it). With normal use, it
is hard to detect any difference between the speed of the different areas
of memory.
-- 
Bruce Evans  (evans@syd.dit.csiro.au)