Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!apple!motcsd!mcdcup!phil
From: phil@mcdcup.UUCP (Phil Weinberg SPS)
Newsgroups: comp.sys.m68k
Subject: Re: 68020 Instr Cache
Message-ID: <9089@mcdcup.UUCP>
Date: 10 Oct 90 00:43:40 GMT
References: <1990Oct9.184632.18064@ariel.unm.edu>
Reply-To: phil@mcdcup.UUCP (Phil Weinberg SPS)
Organization: Motorola Semiconductor Products, Sunnyvale , CA 94086-5303
Lines: 23

In article <1990Oct9.184632.18064@ariel.unm.edu> jstearns@draco.unm.edu (Slix) writes:
>I am seeking information on how to turn the 68020's Instr cache off
>and on via hardware.  The only literature I have been able to find says
>that there is a cache disable pin, but not how to use it.  Does anyone
>know exactly how this pin is used or where to find specs??  I have been told
>that the MC68020 user's manual does not have this info. (hard to believe...)
The "Cache Disable" pin (notCDIS) is discussed on pages 5-8,5-9, and
6-3 of the 68020 Users Manual - Motorola P/N MC68020UM/AD REV 3.It is
also shown on pages 3-97 and 3-98 of the M68000 Family Reference
Manual - Motorola P/N FR68K/D.  As mentioned in the refrences the
usual use of this disable pin is to allow external hardware (emulators)
to be able to monitor the processor's opration on a cycle by cycle basis
without getting faked out by what is happening in the cache.
I'm sure that someone can find some reason to dynamically enable
and disable the on-board cache, but it would not normally be used
in this mode.  Usually the cache is either enabled or disabled and
left that way until some event, such as an emulator trigger, would
require a change.
-- 
<< Usual Disclaimer >>
Phil Weinberg @ Motorola Semiconductor, Sunnyvale, CA 94086-5395 
UUCP:  {hplabs, mot,} !mcdcup!phil
Telephone:  +1 408-991-7385