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From: bryce@cbmvax.commodore.com (Bryce Nesbitt)
Newsgroups: comp.sys.m68k
Subject: Re: 68020 Instr Cache
Message-ID: <15052@cbmvax.commodore.com>
Date: 10 Oct 90 19:12:58 GMT
References: <1990Oct9.184632.18064@ariel.unm.edu> <9089@mcdcup.UUCP>
Reply-To: bryce@cbmvax.commodore.com (Bryce Nesbitt)
Organization: Commodore, West Chester, PA
Lines: 28

In article <9089@mcdcup.UUCP> phil@mcdcup.UUCP (Phil Weinberg SPS) writes:
>In article <1990Oct9.184632.18064@ariel.unm.edu> jstearns@draco.unm.edu (Slix) writes:
>The "Cache Disable" pin (notCDIS) is discussed on pages 5-8,5-9, and
>6-3 of the 68020 Users Manual - Motorola P/N MC68020UM/AD REV 3....
>
>I'm sure that someone can find some reason to dynamically enable
>and disable the on-board cache, 

For a 68030, dynamic use of the cache is standard.  I/O registers 
assert CIIN (cache inhibit in) to prevent read data from getting cached.

The 68030 has a problem, however, with writes in WA mode.  Longword writes
to longword aligned addresses allocate a valid entry in the data cache even
if the hardware asserts CIIN.  Without an MMU you are screwed.  So:

		Read from register (no problem, CIIN works)
		Write long to register (valid entry in D-cache)
		Read from register (byte, word or long).  Boom.  Stale data.

Could a system play a game with CDIS to work around the above problem?
On _read_ of the IO space both CIIN and CDIS would be asserted.  This would
prevent the 68030 from using the stale data it got in step 2.

-- 
|\_/|  . "ACK!, NAK!, EOT!, SOH!"  "Lawyers: America's untapped export market."
{X o} .     Bryce Nesbitt, Commodore-Amiga, Inc.
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