Path: utzoo!attcan!uunet!wuarchive!usc!jarthur!nntp-server.caltech.edu!smoggy!newton From: newton@smoggy.gg.caltech.edu (Mike Newton) Newsgroups: comp.sys.m88k Subject: Emulating other computers on 88K's and Benchmarks Message-ID: Date: 8 Oct 90 04:41:18 GMT References: <1990Oct3.095041.9295@canterbury.ac.nz> Sender: news@nntp-server.caltech.edu Organization: California Institute of Technology, Pasadena Lines: 42 Nntp-Posting-Host: smoggy.gg.caltech.edu The m88k has a fundamental advantage over the other RISC's that I know regarding: Interpetation of code for other processors Compilers for certain very high level languages -- (especially: Prolog) and this is 31 truly general purpose registers. For interpreting code for other machines, or for interpreters in general, it is very helpful to be able to keep all "state" in registers. Otherwise memory accesses and updates are serious problem. For several projects that I've worked on, going from 16-->32 registers would make factors of 30%-250% (the last being an rough guess) difference in performnace. There is also certain advantages with the 88k over the MIPS (an great chip, but only 16 reg.s!) in that more of the paging / address translation lines are accessible. This would ease the work of some translate-on-the fly interpretation routines as well as overlay and self-modifying code detection. That the FP registers are the same as the GP registers might slow down some FP code. This is dependent on the register passing conventions, not the number of registers. IE: though you could divide the 31 into 15 normal and 8 double prec. floating, (which I _beleive_ is the same as MIPS) in reality this would have to be modified for register passing of args and linker registers. On a related topic talked about... : Be careful when you look at m88k performance statistics. In particular, find out: [1] What compiler is being used -- Tom Wood at DG has made _many_ improvements to gcc over the last year. Some of my code runs noticeably faster. [2] The memory model, including wait states. The lower end DG machines have a fair number of wait states -- a fact that surprised me, considering their memory is custom. - mike -- newton@csvax.cs.caltech.edu Beach Bums Anonymous, Pasadena President Caltech 256-80 (Hilo -- it's not just another rainy day!) Pasadena CA 91125 Life's a beach. Then you graduate.