Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!cica!iuvax!ux1.cso.uiuc.edu!pequod.cso.uiuc.edu!dorner From: dorner@pequod.cso.uiuc.edu (Steve Dorner) Newsgroups: comp.sys.next Subject: Re: SOME ADVICE FOR NEXT Message-ID: <1990Oct8.182201.7907@ux1.cso.uiuc.edu> Date: 8 Oct 90 18:22:01 GMT References: <340@atncpc.UUCP> Sender: news@ux1.cso.uiuc.edu (News) Reply-To: dorner@pequod.cso.uiuc.edu (Steve Dorner) Distribution: comp Organization: University of Illinois at Urbana-Champaign Lines: 13 In article melling@cs.psu.edu (Michael D Mellinger) writes: >etc. I think the IBM RS/6000 can do 4 instructions in one clock >cycle(ideally). A CPU that runs at 50MHz and completes 4 instructions >(on average) a cycle is going to give you 200 mips. No, because RISC instructions do less. You have to normalize to VAX 780 mips if you want to make "real" comparisons. (If you really want to make "real" comparisons, you have to try doing YOUR REAL WORK on the machine; even the best benchmark can be very, very deceptive.) -- Steve Dorner, U of Illinois Computing Services Office Internet: s-dorner@uiuc.edu UUCP: uunet!uiucuxc!uiuc.edu!s-dorner